An elementary memory cell of SRAM type (i.e., an SRAM-type elementary memory cell) is a volatile memory cell, that is to say one that loses its data in the event of a power cut, but that offers a very rapid access speed and infinite cycling.
A non-volatile elementary memory cell, for example a memory cell of EEPROM type, allows the data item to be preserved in the event of a power cut but cannot be cycled indefinitely.
A memory cell associating an elementary cell of SRAM type and several non-volatile cells (for example two or four) allows accumulation of the levels of performance of the two approaches, namely the speed and the infinite reliability of the SRAM memory and the nonvolatility of the non-volatile memory, for example the flash or EEPROM memory.
Under normal operating conditions, a data item is written and read to/from a memory cell of this kind in the elementary cell of SRAM type. On the other hand, notably during a power cut, the content of the elementary SRAM cell is transferred to the non-volatile elementary memory cells that are associated therewith.
Then, notably when power returns, the data contained in the non-volatile memory cells are reloaded into the corresponding SRAM elementary memory cell.
Architectures of such memory cells associating SRAM memory and non-volatile memory are described in the documents U.S. Pat. No. 4,132,904, U.S. Pat. No. 4,467,451, U.S. Pat. No. 4,980,859, U.S. Pat. No. 7,164,608 and U.S. Pat. No. 8,018,768. However, these known structures have numerous drawbacks such as notably a complexity of structure and/or the need to have an SRAM cell supporting a high voltage and/or large constraints for the reloading phase of the SRAM cell.